This invention relates to electrical circuitry. More particularly, it is concerned with logic circuits having arrangements for interfacing with logic circuitry operating with different logic levels.
Two widely used, well known logic systems are ECL (emitter-coupled logic) and CMOS (complementary metal oxide semiconductor) logic systems. The logic levels for ECL logic are -1.6 volt and -0.8 volt, and for CMOS the logic levels are 0 volts and +5 volts. The threshold voltage for CMOS logic, that is the voltage at which a CMOS logic circuit triggers from one operating state to another, is +2.5 volts. Since this threshold voltage is outside the operating range of ECL logic, CMOS logic circuitry is not directly compatible with ECL circuitry.
One arrangement for shifting the operating voltages of CMOS logic circuitry to provide a threshold value of -1.2 volts (the same as that required by ECL) is described in U.S. Pat. No. 5,045,730 to Cooperman and Sieber. Although shifting of the operating voltages for the CMOS circuitry provides satisfactory operation under normal conditions, variations in the operating conditions of the CMOS circuitry can lead to unwanted variations in the threshold voltage of the CMOS circuitry. Since the ECL voltage levels are separated by only 800 millivolts, a relatively small change in the threshold voltage of the CMOS circuitry could result in malfunction.